Disc east [1] 1-16 -> Delay East *16 (width 13ns) [2] 1-8 -> PLU-east ch0 1-8 (East inner no-delay) [2] 9-16 -> Nowhere (East outer no-vertex) Disc west [1] 1-16 -> Delay West *16 (width 13ns) [2] 1-8 -> PLU-West ch0 1-8 (West inner no-delay) [2] 9-16 -> Nowhere (West outer no vertex) delay east [1] 1-8 -> PLU-east ch1 1-8 (East inner delay) (delay ~ 12nsec) [1] 9-16 -> Nowhere (East outer vertex) [2] 1-16 -> Time to FERA East *16 [3] 1-16 -> Nowhere delay west [1] 1-8 -> PLU-West ch0 1-8 (West inner vertex) (delay ~ 12nsec) [1] 9-16 -> Nowhere (West outer vertex) [2] 1-16 -> Time to FERA West *16 [3] 1-16 -> Nowhere PLU-east ch0 bit1 (N or more out of 8) -> PLU-3 ch0 bit1 (East-I no delay) PLU-east ch0 bit2 (Sum 2 PMT Top) -> PLU-3 ch0 bit2 (East-I-T no delay) PLU-east ch0 bit3 (N or more out of 8) -> PLU-3 ch1 bit1 (East-I no delay) PLU-east ch0 bit4 (Sum 2 PMT Bottom) -> PLU-3 ch1 bit2 (East-I-B no delay) PLU-east ch0 bit5 (N or more out of 8) -> PLU-4 ch0 bit1 (East-I no delay) PLU-east ch0 bit6 (Sum 2 PMT North) -> PLU-4 ch0 bit2 (East-I-N no delay) PLU-east ch0 bit7 (N or more out of 8) -> PLU-4 ch1 bit1 (East-I no delay) PLU-east ch0 bit8 (Sum 2 PMT South) -> PLU-4 ch1 bit2 (East-I-S no delay) PLU-east ch1 bit1 (N or more out of 8) -> PLU-3 ch0 bit3 (East-I delay) PLU-east ch1 bit2 (Sum 2 PMT Top) -> PLU-3 ch0 bit4 (East-I-T no delay) PLU-east ch1 bit3 (N or more out of 8) -> PLU-3 ch1 bit3 (East-I delay) PLU-east ch1 bit4 (Sum 2 PMT Bottom) -> PLU-3 ch1 bit4 (East-I-B no delay) PLU-east ch1 bit5 (N or more out of 8) -> PLU-4 ch0 bit3 (East-I delay) PLU-east ch1 bit6 (Sum 2 PMT North) -> PLU-4 ch0 bit4 (East-I-N no delay) PLU-east ch1 bit7 (N or more out of 8) -> PLU-4 ch1 bit3 (East-I delay) PLU-east ch1 bit8 (Sum 2 PMT South) -> PLU-4 ch1 bit4 (East-I-S no delay) PLU-west ch0 bit1 (N or more out of 8) -> PLU-3 ch0 bit5 (West-I no delay) PLU-west ch0 bit2 (Sum 2 PMT Top) -> PLU-3 ch0 bit6 (West-I-T no delay) PLU-west ch0 bit3 (N or more out of 8) -> PLU-3 ch1 bit5 (West-I no delay) PLU-west ch0 bit4 (Sum 2 PMT Bottom) -> PLU-3 ch1 bit6 (West-I-B no delay) PLU-west ch0 bit5 (N or more out of 8) -> PLU-4 ch0 bit5 (West-I no delay) PLU-west ch0 bit6 (Sum 2 PMT North) -> PLU-4 ch0 bit6 (West-I-N no delay) PLU-west ch0 bit7 (N or more out of 8) -> PLU-4 ch1 bit5 (West-I no delay) PLU-west ch0 bit8 (Sum 2 PMT South) -> PLU-4 ch1 bit6 (West-I-S no delay) PLU-west ch1 bit1 (N or more out of 8) -> PLU-3 ch0 bit7 (West-I delay) PLU-west ch1 bit2 (Sum 2 PMT Top) -> PLU-3 ch0 bit8 (West-I-T no delay) PLU-west ch1 bit3 (N or more out of 8) -> PLU-3 ch1 bit7 (West-I delay) PLU-west ch1 bit4 (Sum 2 PMT Bottom) -> PLU-3 ch1 bit8 (West-I-B no delay) PLU-west ch1 bit5 (N or more out of 8) -> PLU-4 ch0 bit7 (West-I delay) PLU-west ch1 bit6 (Sum 2 PMT North) -> PLU-4 ch0 bit8 (West-I-N no delay) PLU-west ch1 bit7 (N or more out of 8) -> PLU-4 ch1 bit7 (West-I delay) PLU-west ch1 bit8 (Sum 2 PMT South) -> PLU-4 ch1 bit8 (West-I-S no delay) PLU-3 ch0 bit0 (East-I-nd & East-I-d & West-I-nd & Wast-I-d) -> Trigger with vertex PLU-3 ch0 bit1 (East-I-nd & West-I-nd) -> Trigger without vertex PLU-3 ch0 bit2 (East-I-T-nd & East-I-T-d & West-I-nd & Wast-I-d) -> Scalar (Blue Top with vertex) PLU-3 ch0 bit3 (East-I-nd & East-I-d & West-I-B-nd & Wast-I-B-d) -> Scalar (Yellow Bottom with vertex) PLU-3 ch0 bit4 (East-I-T-nd) -> Scalar (East Top) PLU-3 ch0 bit5 (West-I-T-nd) -> Scalar (West Bottom) PLU-3 ch0 bit6 (East-I-T-nd & East-I-T-d & West-I-B-nd & Wast-I-B-d) -> Scalar? (Top-Bottom vertex) PLU-3 ch1 bit0 (East-I-nd & East-I-d & West-I-nd & Wast-I-d) -> Scalar (Trigger with vertex) PLU-3 ch0 bit1 (East-I-nd & West-I-nd) -> Scalar (Trigger without vertex) PLU-3 ch1 bit2 (East-I-B-nd & East-I-B-d & West-I-nd & Wast-I-d) -> Scalar (Blue Bottom with vertex) PLU-3 ch1 bit3 (East-I-nd & East-I-d & West-I-T-nd & Wast-I-T-d) -> Scalar (Yellow Top with vertex) PLU-3 ch1 bit4 (East-I-B-nd) -> Scalar (East Bottom) PLU-3 ch1 bit5 (West-I-B-nd) -> Scalar (West Top) PLU-3 ch1 bit6 (East-I-B-nd & East-I-B-d & West-I-T-nd & Wast-I-T-d) -> Scalar? (Bottom-Top vertex) PLU-4 ch0 bit2 (East-I-N-nd & East-I-N-d & West-I-nd & Wast-I-d) -> Scalar (Blue North with vertex) PLU-4 ch0 bit3 (East-I-nd & East-I-d & West-I-S-nd & Wast-I-S-d) -> Scalar (Yellow North with vertex) PLU-4 ch0 bit4 (East-I-N-nd) -> Scalar (East North) PLU-4 ch0 bit5 (West-I-N-nd) -> Scalar (West South) PLU-3 ch1 bit6 (East-I-N-nd & East-I-N-d & West-I-S-nd & Wast-I-S-d) -> Scalar? (North-South vertex) PLU-4 ch1 bit2 (East-I-S-nd & East-I-S-d & West-I-nd & Wast-I-d) -> Scalar (Blue South with vertex) PLU-4 ch1 bit3 (East-I-nd & East-I-d & West-I-N-nd & Wast-I-N-d) -> Scalar (Yellow North with vertex) PLU-4 ch1 bit4 (East-I-N-nd) -> Scalar (East South) PLU-4 ch1 bit5 (West-I-N-nd) -> Scalar (West North) PLU-3 ch1 bit6 (East-I-S-nd & East-I-S-d & West-I-N-nd & Wast-I-N-d) -> Scalar?(South-North vertex)