Analysis of FermiLab test beam data taken in May of 2007 , based on run #34

(zom in)

  1. Detector layout

  2. Example of U-plane raw ADC spectra for connected & unconnected strip for the same chip. Pedestal peak (& ped fit range) is defined by threshold set at Y>15 & width>10 chan.

  3. Example of V-plane raw ADC spectra

  4. Example of correlation between the same channels, U-plane

  5. Correlation for V-plane.

  6. Distribution of pedestal position and width for all channels from the U-plane. Pedestal QA criteria were set as: PDF for all channels in diskB U-plane pages1-15, V-=plane:pages 26-50. Channels with failed QA ar marked in red.

  7. U-plane pedestals: position & width. Good 190 of 192.

  8. V-plane pedestals: position & width. Good 125 of 192.

  9. All 2x192 spectra gated with strip BV73 to have ADC<20. PDF for all channels in diskB
    Result: channels in the same chip have also ADC=0, but other chips have ~normal spectra.

  10. Apply chip-based pedestal correction
    Method: drop bad strips, drop rawADC<=0, calculate average per chip, subtract,add 600.

  11. U-plane pedestals: position & width.

  12. V-plane pedestals: position & width.

  13. Iteration2: Drop few channels with large sigma: U64, U128, V0, V62-64
    List of masked strips
    PDF for all channels in diskB After iteration 2

  14. U-plane pedestals: position & width. Good 190 of 192.

  15. V-plane pedestals: position & width. Good 125 of 192.

  16. Examples of improved spectra, very good case in the moddle of a chip. Raw spectra in blue, after iteration 2 in green


    And not so good, at the edges of a chip.



  17. Now is time to correct for capacitor address. Below is distribution of used addresses for one detector. No correlation w/ ADC is observed.

  18. capID vs. ADC for strip U34

  19. capID vs. ADC for strip U60