Readout Board FPGA Record Description

1. Introduction

This record is in charge of the control of the Readout Board FPGA chip. One instance of this record controls one Readout Board.

2. Fields Description

Field Name
Summary
Type
Comments

VAL

Command

enum

see the list of commands below (input)

RDNB

Readout Board Number

short

Between 0 and 3. (input)

BTYP

Board type

uchar

default : 0x2 (output)

VER1

FPGA Code version 1

uchar

Version of the code inside the FPGA (output)

VER2

FPGA Code version 2

uchar

LMDY

Last modif. day

uchar

Date of last modification of the code. (output)

LMMH

Last modif. month

uchar

LMYR

Last modif. year

ushort

TML1

Transp. Mode ladder 1

uchar

Numbers of the two ladders to put in transparent mode (input)

TML2

Transp. Mode ladder 2

uchar

PMEN

PM enable

uchar

'1' enable '0' disable, see Readout Board documentation (output)

PCEN

PC enable

uchar

'1' enable '0' disable, see Readout Board documentation (output)

PHDL

PM Hold Delay

uchar

Value of the HOLD signal delay if PM, steps of 33,33ns (30MHz clock) (input)

L2AC

L2 accept

uchar

'1' wait for 'L2accept' trigger, '0' do not wait (input)

FILL

Filling type

uchar

'0' 64x512=TPC, '1' 64x256, '2' 16x768=SSD, '3' 64x512 (input)

ITXO

Init TXO readout

uchar

Reset TXO ('1'=reset) (input)

THDL

Trigger Hold Delay

uchar

Value of the HOLD signal delay if normal trigger, steps of 33,33ns (30MHz clock) (input)

CADL

Calib Hold Delay

uchar

Value of the HOLD signal delay if calibration trigger, steps of 33,33ns (30MHz clock) (input)

CFGN

Configuration Number

uchar

16 bits (input)

TRBB

Trigger Busy Back

uchar

'1' operation in progress, '0' ready (output)

TRSB

Trigger Status Back

uchar

'1' Slow Control , '0' DAQ (input)

FETS

FE tdo sel

uchar

'1' complete Jtag chain, '0' Readout Board alone. (input)

TRCK

Trigger Clock ok

uchar

'1' OK, '0' not present (input)

TCKS

Trg Clk Alarm Severity

severity

default : MAJOR (input)

TMPV

Temperature validity

uchar

'1' valid, '0' not valid (output)

TMP1

Temperature 1

ushort

value in degres Celsius (output)

TMP2

Temperature 2

ushort

value in degres Celsius (output)

TALM

Temperature Alarm

uchar

'1' alarm, '0' no alarm

TALS

Temp. Alarm Severity

severity

default : MAJOR (input)

DTSD

Detector side(P or N)

uchar

'1' P, '0' N (output)

GLER

Giga link error

uchar

'1' Error, '0' OK (output)

GLAS

G-link Alarm Severity

severity

default : MAJOR (input)

LUEV

Latchup Event

uchar

'1' Latchup, '0' no latchup (output)

LUCT

Latchup Counter

uchar

set to zero when 'Trigger Status Back' is active (output)

LUAS

Latchup Alarm Severity

severity

default : MAJOR (input)

RDLC

ReadoutBoard location

uchar

5 bits (output)

FPST

FPGA Program status

ushort

'0'=OK (output)

FPAL

FPGA Alarm

uchar

'1' alarm, '0' no alarm (output)

FPAS

FPGA Alarm Severity

severity

default : MAJOR (input)

FPNM

FPGA Program Name

string

filename of the FPGA program (JBC file) (input)

FPPT

FPGA Program Path

string

directory of the FPGA program. (input)

JCLK

JTAG Clock Frequency

ulong

in Hertz (automatically converted to the nearest possible value). (input)

CXID

Readout Board ID

uchar

Value of the Jtag ID register (output)

NBEV

Number of events

ushort

Trigger event counter (output)

3. Commands

The 'VAL' field of this record can have one of the following values :

NOP

Do nothing.

CONFIG

Set the 'config' register of the Readout Board. This register is composed of the fields : 'THDL' 'CADL' 'PHDL' 'TML1' 'TML2' 'ITXO' 'FILL' and 'L2AC'.

STATUS

Read the 'status' register of the Readout Board and update the 'RDLC' 'LUEV' 'GLER' 'DTSD' 'TMPV' 'TRCK' 'TRBB' 'PCEN' and 'PMEN' Fields. Read the 'latchup counter' register and update the 'LUCT' field. Read the 'id' register and update the 'CXID' field. read the 'number of event' register and update the 'NBEV' field. If the temperature is valid ('TMPV' field) read the 'temperature' registers and update the 'TMP1' and 'TMP2' fields.

VERSION

Read the 'version' register of the Readout Board and update the 'LMYR' 'LMMH' 'LMDY' 'VER1' 'VER2' and 'BTYP' fields

CONTROL

Get the Readout Board in 'Full Control' mode (the full Jtag chain can be accessed)

DAQ

Get the Readout Board in 'Daq' mode (only the Readout Board can ce accessed through Jtag)

FPGA

Program the FPGA of the Readout Board, ADC Boards and Connection Board.

RESET

Given the JTAG frequency requested by the user, it calculates the nearest possible frequency and does a 'hard' reset (TRSTB reset).

ON

Power on all the Readout Boards.

OFF

Power off all the Readout Boards.

note : after the execution of each of these commands, the 'VAL' field is set to 'NOP'. But there are two exception to this rule : if the programmation of the FPGA failed, the 'VAL' field is set to 'CONFIG' and if the 'CONTROL' command failed (unable to get in 'Full Control' mode) the 'VAL' field is set to 'DAQ'.

4. Source Files

in '/star/tools/control/epics/R3.12-LBL.4/ssdApp/src/'

ReadoutFPGARecord.ascii : Record fields description

jtagCommon.c, jtagCommon.h, jtagReadout.c, jtagReadout.h : Harware layer.

recReadoutFPGA.c : Record support routines.