Requirement: Clock Signal Definition
The SCA clock shall be a single differential modified PECL line which carries the write clock (27 MHz) during sampling and the read clock (3 MHz) during readout.
Differential PECL (positive emitter coupled logic) levels are used because of low switching levels (and therefore reduced EMI), high speed capability and the ability to drive a large number of SCAs on a single line. Different rates are used to provide the proper clocking frequency on a single line to avoid additional traces (2 traces per differential clock line). Previous SCA devices have used similar clock drives so the risk is low. The modification required to the PECL level is addressed in the next paragraph.
Requirement: Adjustment to PECL State Voltages
A logic 0 shall be less than 3.4 V. A logic 1 shall be greater than 4.1 V.
The definition of PECL levels includes an adjustment because the SCA operates at 5 V rather than the standard 5.2 V normally used for PECL.