Requirement:
The DAQ system will perform SVT channel pedestal value calibrations at the receiver board level. It will be capable of accumulating and calculating ADC pedestal offset values for each SVT anode's time bucket and loading internal pedestal memory. The resulting pedestal values, if requested, will be sent through the normal data stream for archiving or inspection. (Time limit?)
Justification:
Pedestal calibration events are essentially black SVT events and are very large. During normal operation, there is little need to inspect or save data from individual pedestal calibration events. They are primarily used as inputs to a simple algorithm that produces individual channel offset averages that can be loaded into local pedestal memory on the receiver boards. By placing the pedestal calibration algorithm as far upstream as possible, we lessen the need to move these large black events through the system. Thus, pedestal calibration is faster, easier and, hopefully, performed more frequently.
During debugging or when individual channel sigma's appear unacceptably large, pedestal offset values (i.e. the result of the pedestal calibration algorithm) can be inserted into the data stream for recording or further analysis. The only need for uploading pedestal values would be to artificially supress the data from a single channel. As there will be other DAQ system mechanisms to accomplish this, there is no need, during normal operations, to upload pedestal memory.