The 8-bit ID headerSSSSSRRR
for an RDO location, position
RRR=[1,6] on sector SSSSS=[1,24], is enforced
by a plug-in header tied to the incoming power cord.
Several PROM's on each RDO program the
Xilinx chips; it is crucial that the correct versions be used.
The intermittant configuration problems, related to faster PROM's and
the trigger cable tending to pull the +5V level of an unpowered board
to about +0.75V, seen on some boards are now understood and can be
prevent by terminating the PROM clock line with a 150-ohm resistor and
using another resistor (about 120 ohm, 1/2 watt) across the filter cap.
on the main 5V regulator to pull down the unpowered voltage to about
There are a number of LED's
on each RDO to show the status of:
Clock signal from trigger cable
Triggers from trigger cable
Each RDO is powered by three pairs of leads at about +8V, -8V and
(TPC) ground. Power supplies for 3 readout boards are mounted in
one chasis. The + and - currents are similar, so the ground lead
current is small; if it is badly connected, malfunctions can be
Noise and pedestal values have shown a surprising sensitivity to
RDO grounding conditions. The gold-plates sheet behind the FEE
cards; the gold-plated FEE mounting brackets; and the insulated
cable connectors represent part of the solution.
All RDO sections share a common bus. Each section has its own
voltage regulators and FPGA chip. Meaningless "ghost" data is read
from non-existent sections, giving the appearance of 9 sections and
1152 channels on all RDO's.
Voltage regulator cooling:
Unnecessary stainless steel and Sil-Pad washers have been removed from
the main +5V regulator to lower its operating temperature. Thermal
resistivities of some materials: