SVT Level 3 Trigger - Technical Issues
Person Responsible: J. Schambach, University of Texas, Austin
Last Update - August 30, 1995
The SVT L3 technical issues can be divided into roughly 4 separate areas:
- Space Point Finding
- Tracking
- Vertex Finding
- Whole L3 Chain Simulation
In the following the specifics for these areas are explained.
- Space point finding
- Tasks for this item include:
- Generate slow simulator output before ASIC with noise
- Optimize parameters used in the ASIC simulation:
- sequence finding (different cuts on 2 threshold model)
- 10->8bit conversion (different translation functions),
- varying pedestal simulation
- varying gain correction
- Generate data sets (input and output) for ASIC tester
- Investigate cluster finding efficiencies and merged cluster resolution
- Investigate space point finding efficiencies and resolutions
- Investigate alternative cluster and space point finding algorithms
- Time different algorithms on i960, evaluate dependence of timing on
wafer number, data sets, ...
- Tracking
- Tasks for this item include:
- Investigate efficienies of grouper algorithm as f of different cuts,
data sets, hardware configurations
- Investigate alternative tracking algorithms
- Time algorithms on different L3 hardware (alpha, PPC) and
different data sets,
investigate timing variations, cut optimization
- Vertex Finding
- Tasks for this item include:
- Investigate different algorithms
- Time of algorithms on L3 hardware (alpha, PPC)
- Whole L3 chain simulation
- Simulate whole L3 chain:
- Nine i960's (for one octant) -> one L3 processor for one octant
- Eight octant L3 processors -> one global L3 processor