STAR Trigger System Logic Documents


Expand/Collapse Item Requirements

     Trigger System Logic Requirements Document   

TCU_requirements for 2002
TCU_requirements for 2008
RCC2_requiremnts for 2011
Scalar2 requirements for 2010
DSM2 Requirements
STP2 Requirements

Expand/Collapse Item Context Diagrams

Expand/Collapse Item Interfaces

       Bit List from Scaler Patch panel GLINK to RHIC Scalers (This file is in .pdf format)   

       STAR Trigger VME Board Base Address List (This file is in .pdf format)   

       STAR Trigger Detector Bit List   

Expand/Collapse Item Simulations

     Trigger Data Flow Simulation - (10-10-95)   

Expand/Collapse Item Electronics Schematics / Drawings

     NOTE: All schematics are in PDF format unless otherwise stated   

     Time-to-Analog Converter (TAC)   

       TRG410 - Board Schematics   

     Data Storage and Manipulation Board (DSM)   

       TRG400 - DSM   

       TRG401 - DSMI   

       TRG402 - TDSMI   

       TRG403 - TOF-DSMI   

       The DSMI and TDSMI share the same front panel and cable clamps   

       TRG051-A-1 Front Panel   

       TRG052-A-1 Cable Clamp Bars   

       TRG053-A-1 Cable Clamp (long)   

       TRG054-A-1 Cable Clamp (short)   

     Trigger Control Unit (TCU) Version 4 - 2013   

       Motherboard Schematics   

       Daughterboard Schematics   

       Routing Board Schematics   

       TRG501 TCUI Board Schematics   

       NOTE: The TCU is a 2-slot module.

The Motherboard uses the existing DSMI previously used by the last DSM (see TRG401 above).

The Routing Board uses the existing TCUI.   

     P3 Driver Card (PDC)   

       TRG502 Board Schematics   

     RHIC Clock and Control Board (RCC) Version 2 - 2012   

       RCC2 Board Schematics   

       RCF2 Board Schematics   

     Scaler   

       TRG420 Board Schematics   

     Scaler router mother (RAT)   

       RAT Mother Board Schematics   

     Scaler router daughter (RAT)   

       RAT Daughter card Schematics   

     STP   

       Concentrator Schematic   

       Level2 card Schematic   

       PCI Mezzanine Card Schematic   

     Level Adapter   

       TRG450 Board Schematics   

     20-bit Fiber Tx/Rx   

       TRG560-D-1 STAR Trigger 20-bit Gigalink Fiber Transmitter Schematic   

       TRG561-D-1 STAR Trigger 20-bit Gigalink Fiber Receiver Schematic   

Expand/Collapse Item Level 0 Schematics / Drawings

     General TSL   

     DSM Tree - 2005 (This file is in .pdf format)   

     Vertex Branch Detail - 2005 (This file is in .pdf format)   

     Barrel EMC Detail - 2003 (This file is in .pdf format)   

     Endcap EMC Detail - 2003 (This file is in .pdf format)   

     Cables Maps   

     BBC Crate Cable Map - run 18   

     BEMC East Crate (BCE) Cable Map - run 5->18   

     BEMC West Crate (BCW) Cable Map - run 2->18   

     BEMC Crate (BC1) Cable Map - run 9->18   

     BBQ Crate Cable Map - run 11->18   

     EPD Crate (EPQ) Cable Map - run 17   

     FMS Crate (FMS) Cable Map - run 15->17   

     L1 Crate Cable Map - run 18   

     MIX Crate Cable Map - run 18   

     MXQ Crate Cable Map - run 17->18   

     Scaler Cable Map (this file is in .pdf format)   

     Scaler Panel Cable Map (this file in .pdf format)   

     Crate Layouts   

     BBC Crate Layout - run 9 -> 18   

     BBC Digitizer Crate (BBQ) Layout - run 11->18   

     BEMC East Crate (BCE) Layout - run 4->18   

     BEMC West Crate (BCW) Layout - run 2->18   

     BC1 Crate (BEMC Layer 1: EndCap Layer 0&1) Layout - run 9->18   

     EQ1 (first EPD QT Crate) Layout - run 18   

     EQ2 (second EPD QT Crate) Layout - run 18   

     EQ3 (third EPD QT Crate) Layout - run 18   

     FMS Crate (FMS) Crate Layout - run 15->18   

     L1 Crate Layout - run 13->18   

     MIX Crate Layout - run 16 -> 18   

     MXQ (MIX Digitizer Crate) - run 17->18   

     Timing   

     Trigger Level 0 Timing from Interaction to TCD - 2003 (This file is in .pdf format)   

     Trigger Level 0 Timing from Interaction to TCD - 2001 (This file is in .pdf format)   

     Trigger Timing Blocks and Cable Delays (This file is in .pdf format)   

     DSM to DSM Timing (This file is in .pdf format)   

     CDB to DSM Timing (This file is in .pdf format)   

     TCU Internal Timing (This file is in .pdf format)   

     RCF-to-DSM Connection List (This file is in .pdf format)   

Expand/Collapse Item Software

       Diagram of Trigger Software: Processes, CPUs and Data Flow (This file is in .pdf format)   

       STAR TRG VME Software Documentation -   

     TIER1 FILES   

     Dictionary File for current Tier1 file
(to view earlier Tier1 Dictionary files, go to http://www.star.bnl.gov/public/trg/TSL/Software/Tier1/"filename")   

     QT ALGORITHMS   

     VERTEX Branch - ZDC (ZD001) Hybrid Algorithm   

     VERTEX Branch - VPD (VP001,VP002)   

     VERTEX Branch - BBC small tiles (BB001,BB002)   

     VERTEX Branch - BBC LARGE tiles (BB003)   

     MTD Branch - MTD (MT001->4)   

     MTD Branch - VPD (VP003,VP004)   

     PP2PP (PP001)   

     ZDCSMD (PX001)   

     FMS Branch - QT1->4 Heavy-Ion Running   

     FMS Branch - QT1->4 Run2015 PP   

     DSM ALGORITHMS   

     Run-Specific Physics Algorithms   

     NOTE: These links point to the current documentation. Previous versions are archived at /afs/rhic.bnl.gov/star/doc/www/trg/TSL/Software/   

     VERTEX Branch - ZDC, BBC and VPD Detectors for 2016 200 GeV Heavy-Ion Running   

     VERTEX Branch - ZDC, BBC and VPD Detectors for 2016 d+Au Running   

     VERTEX Branch - ZDC, BBC and VPD Detectors for 2017 PP Running   

     VERTEX Branch - ZDC, BBC, VPD and EPD Detectors for 2017 53 GeV Heavy-Ion Running   

     EMC Branch - Barrel and Endcap Calorimeters for AA Running   

     EMC Branch - Barrel and Endcap Calorimeters for pp Running   

     FMS Algorithms   

     TOF Branch: TOF, MTD and PP2PP Algorithms for AA Running   

     TOF Branch: TOF, MTD and PP2PP Algorithms for pp Running   

     Fixed Algorithms   

     TPC Readout Bitmask Selection   

     Laser Trigger, Zero-Bias and Random Bit Algorithm for the 2010 AuAu Run   

     First Bunch Crossing DSM   

     Second Bunch Crossing DSM   

     l1_vt201_2010_a.rbt - Beam Tuning Algorithm for Vertex Detectors   

     debug_sel2chn_2009_a.rbt - Debugging Algorithm   

Expand/Collapse Item Testing

     General TSL   

     DSM   

       DSM Hardware Production and Testing Procedure (This file is in .pdf format)   

       DSM Hardware Production Logsheet (This file is in .pdf format)   

     TCU   

Expand/Collapse Item Discussions / Archive

Expand/Collapse Item Manuals

     RCC2 User Manual   

     RCC2 Memory Map   

     Scalar Board User Manual   

     Scaler Manual   

     DSM Memory Map   

     DSM Algorithm Compilation   

     QT Memory Map   

     QT Algorithm Compilation   

     TAC Operation   

     TCU-4 Memory Map   

     TCU-4 Counter Description   

     TCU-4 Software Flow   

     TCU-4 Hardware Description   

     Trigger Timing Diagnostics   

     Tier1 File Construction   

     Tier1 File - Auxilliary Files   

     Trigger Level0_Timing Setup   

     Trigger Board Hardware Switch Settings   

     DIB Board Switch Settings (This file is in .pdf format)   

     CDB Board Switch Settings (This file is in .pdf format)   

     DSMI/TDSMI Board Switch Settings (This file is in .pdf format)   

     DSM Board Switch Settings (This file is in .pdf format)   

     TCUI Board Switch Settings (This file is in .pdf format)   

     TCU Board Switch Settings (This file is in .pdf format)