TCU_requirements for 2002
TCU_requirements for 2008
RCC2_requiremnts for 2011
Scalar2 requirements for 2010
QTI2 Requirements
DSM2 Requirements
STP2 Requirements
QT32D Requirements
STAR Trigger VME Board Base Address List (This file is in .pdf format)
STAR Trigger Detector Bit List
Time-to-Analog Converter (TAC)
Data Storage and Manipulation Board (DSM)
The DSMI and TDSMI share the same front panel and cable clamps
TRG054-A-1 Cable Clamp (short)
Trigger Control Unit (TCU) Version 4 - 2013
NOTE: The TCU is a 2-slot module.
The Motherboard uses the existing DSMI previously used by the last DSM (see TRG401 above).
The Routing Board uses the existing TCUI.
P3 Driver Card (PDC)
RHIC Clock and Control Board (RCC) Version 2 - 2012
Scaler
Scaler router mother (RAT)
Scaler router daughter (RAT)
STP
Level Adapter
20-bit Fiber Tx/Rx
TRG560-D-1 STAR Trigger 20-bit Gigalink Fiber Transmitter Schematic
TRG561-D-1 STAR Trigger 20-bit Gigalink Fiber Receiver Schematic
DSM Tree - 2005 (This file is in .pdf format)
Vertex Branch Detail - 2005 (This file is in .pdf format)
Barrel EMC Detail - 2003 (This file is in .pdf format)
Endcap EMC Detail - 2003 (This file is in .pdf format)
Cables Maps
BEMC East Crate (BCE) Cable Map - run 5->18
BEMC West Crate (BCW) Cable Map - run 2->18
BEMC Crate (BC1) Cable Map - run 9->18
BBQ Crate Cable Map - run 11->18
EPD Crate (EQ1, EQ2, EQ3, & EQ4) Cable Maps - run 23
FMS Crate (FMS) Cable Map - run 15->17
MXQ Crate Cable Map - run 17->18
Scaler Cable Map (this file is in .pdf format)
Scaler Panel Cable Map (this file in .pdf format)
Crate Layouts
BBC Digitizer Crate (BBQ) Layout - run 22
BEMC East Crate (BCE) Layout - run 22
BEMC West Crate (BCW) Layout - run 22
BC1 Crate (BEMC Layer 1: EndCap Layer 0&1) Layout - run 22
EQ1 (first EPD QT Crate) Layout - run 23
EQ2 (second EPD QT Crate) Layout - run 23
EQ3 (third EPD QT Crate) Layout - run 23
EQ4 (fourth EPD QT Crate) Layout - run 23
MXQ (MIX Digitizer Crate) - run 23
Timing
Trigger Level 0 Timing from Interaction to TCD - 2003 (This file is in .pdf format)
Trigger Level 0 Timing from Interaction to TCD - 2001 (This file is in .pdf format)
Trigger Timing Blocks and Cable Delays (This file is in .pdf format)
DSM to DSM Timing (This file is in .pdf format)
CDB to DSM Timing (This file is in .pdf format)
TCU Internal Timing (This file is in .pdf format)
RCF-to-DSM Connection List (This file is in .pdf format)
STAR TRG VME Software Documentation -
TIER1 FILES
Dictionary File for current Production Tier1 file
Dictionary File with current Production STP2, DSM2, and QTD configuration
TCU Bit List for current Production Tier1 file
(to view earlier Production Tier1 fiiles go to http://www.star.bnl.gov/public/trg/TSL/Software/Tier1/"filename")
Dictionary File for current Cosmic Tier1 file
TCU Bit List for current Cosmic Tier1 file
(to view earlier Cosmic Tier1 files, go to http://www.star.bnl.gov/public/trg/TSL/Software/Tier1/"filename")
QT ALGORITHMS
Algorithm 6f - ZDC (ZD001) Hybrid Algorithm
Run 19: Used by ZDC
Algorithm 6d - Fastest TAC and ADC Sum
Run 19: Used by BBC, VPD and VPD-MTD
Algorithm 76 - Mean TAC, ADC Sum and Hit Count
Run 19: Not Used
Algorithm 78 - Fastest TAC and Hit Count
Run 19: Used by EPD inner tiles
Algorithm 7a - Hit Count
Run 19: In test for EPD outer tiles
Algorithm 64 - ADC Sum
Run 19: Used by EPD outer tiles
Algorithm 7c - HT + Integer RHIC Clock Delay
Test Pulse Algorithm. Can be used by any QTB board.
DSM ALGORITHMS
Run-Specific Physics Algorithms
NOTE: These links point to the current documentation.
Previous versions are archived at /afs/rhic.bnl.gov/star/doc/www/trg/TSL/Software/
VERTEX Branch for low-energy (BES) Heavy-Ion Running
VERTEX Branch for 200 GeV Heavy-Ion Running
EMC Branch - Barrel and Endcap Calorimeters for AA Running
EMC Branch - Barrel and Endcap Calorimeters for pp Running
TOF Branch: TOF, MTD and PP2PP Algorithms for Beam Running
TOF Branch: TOF, MTD and PP2PP Algorithms for Cosmic Ray Running
Fixed Algorithms
Laser Trigger, Zero-Bias and Random Bit Algorithm for the 2010 AuAu Run
l1_vt201_2010_a.rbt - Beam Tuning Algorithm for Vertex Detectors
debug_sel2chn_2009_a.rbt - Debugging Algorithm
Timing Breakdown for STAR Trigger (30May03)
Preliminary Description of Level 2 for 2002 (26 April 02)
Trigger Data Description for 2002 (21Mar02)
Trigger Data for 2002 (19Mar02)
Online Connections for May 1998 System Test
Trigger Level 0 Architecture: TCU and DSM Boards
Trigger Level 1 and 2 Architecture
Preliminary Draft of Test for TCU Board
Preliminary Draft of Test for DSM Board
STAR Trigger Software and Monitoring Interface
DSM Board Scheduling (11-16-94)
Trigger Action on STAR ONL Request
Proposed TRG VME/ONL Interface (18Oct00)
DSM2_QTD_STP2_Configuration File Manual
DSM2_QTD_STP2_Run Control Node Manual
Trigger Board Hardware Switch Settings
DIB Board Switch Settings (This file is in .pdf format)
CDB Board Switch Settings (This file is in .pdf format)
DSMI/TDSMI Board Switch Settings (This file is in .pdf format)
DSM Board Switch Settings (This file is in .pdf format)
TCUI Board Switch Settings (This file is in .pdf format)
TCU Board Switch Settings (This file is in .pdf format)