Bunch Crossing Counter DSM Algorithm

 

12th October 2001

 

Input Bits

 

 

Input Channel

 

 

Bit Description

0:1

Unused

2

Bit 0 RHIC synchronization bit

Bits 1:15 - Unused

3:7

Unused

 

 

Registers

 

 

Register

 

 

Register Description

0

Lower 16 bits of initial counter value.

1

Upper 16 bits of initial counter value.

2

1 bit switch for using, or not, the RHIC synchronization bit

 

 

Output Bits

 

 

Bit

 

 

Description

Bits 0:31

Current counter value

 

Internal Logic