StRoot: RTS/include/SECTOR/uniLib.h Source File

00001 #ifndef _UNI_LIB_H_
00002 #define _UNI_LIB_H_
00003 
00004 
00005 #include <vxWorks.h>
00006 
00007 #include <SECTOR/universe.h>    /* from the BSP */
00008 
00009 /*
00010         the main Universe structure is meant to be used as
00011         a pointer only and is carefully constructed so that
00012         the offsets match the actual registers!
00013         DO NOT CHANGE!
00014         The various "rx" registers are "Universe reserved".
00015 */
00016 
00017 /* for Universe version I */
00018 struct uniStruct {
00019 
00020 volatile UINT32    PCI_ID ;
00021 volatile UINT32    PCI_CSR      ;
00022 volatile UINT32    PCI_CLASS    ;
00023 volatile UINT32    PCI_MISC0    ;
00024 volatile UINT32    PCI_BS       ;
00025 volatile UINT32    PCI_BS1      ;
00026 int r1[9] ;
00027 volatile UINT32    PCI_MISC1    ;
00028 int r2[48] ;
00029 volatile UINT32    LSI0_CTL     ;
00030 volatile UINT32    LSI0_BS      ;
00031 volatile UINT32    LSI0_BD      ;
00032 volatile UINT32    LSI0_TO      ;
00033 int r3 ;
00034 volatile UINT32    LSI1_CTL     ;
00035 volatile UINT32    LSI1_BS      ;
00036 volatile UINT32    LSI1_BD      ;
00037 volatile UINT32    LSI1_TO      ;
00038 int r4 ;
00039 volatile UINT32    LSI2_CTL     ;
00040 volatile UINT32    LSI2_BS      ;
00041 volatile UINT32    LSI2_BD      ;
00042 volatile UINT32    LSI2_TO      ;
00043 int r5 ;
00044 volatile UINT32    LSI3_CTL     ;
00045 volatile UINT32    LSI3_BS      ;
00046 volatile UINT32    LSI3_BD      ;
00047 volatile UINT32    LSI3_TO      ;
00048 int r6[9] ;
00049 volatile UINT32    SCYC_CTL     ;
00050 volatile UINT32    SCYC_ADDR    ;
00051 volatile UINT32    SCYC_EN      ;
00052 volatile UINT32    SCYC_CMP     ;
00053 volatile UINT32    SCYC_SWP     ;
00054 volatile UINT32    LMISC                ;
00055 volatile UINT32    SLSI         ;
00056 volatile UINT32    L_CMDERR     ;
00057 volatile UINT32    LAERR        ;
00058 int r7[3] ;
00059 volatile UINT32    LSI4_CTL     ;
00060 volatile UINT32    LSI4_BS      ;
00061 volatile UINT32    LSI4_BD      ;
00062 volatile UINT32    LSI4_TO      ;
00063 int r33 ;
00064 volatile UINT32    LSI5_CTL     ;
00065 volatile UINT32    LSI5_BS      ;
00066 volatile UINT32    LSI5_BD      ;
00067 volatile UINT32    LSI5_TO      ;
00068 int r43 ;
00069 volatile UINT32    LSI6_CTL     ;
00070 volatile UINT32    LSI6_BS      ;
00071 volatile UINT32    LSI6_BD      ;
00072 volatile UINT32    LSI6_TO      ;
00073 int r53 ;
00074 volatile UINT32    LSI7_CTL     ;
00075 volatile UINT32    LSI7_BS      ;
00076 volatile UINT32    LSI7_BD      ;
00077 volatile UINT32    LSI7_TO      ;
00078 int r77[5] ;
00079 volatile UINT32    DCTL ;
00080 volatile UINT32    DTBC ;
00081 volatile UINT32    DLA          ;
00082 int r8 ;
00083 volatile UINT32    DVA          ;
00084 int r9 ;
00085 volatile UINT32    DCPP ;
00086 int r10 ;
00087 volatile UINT32    DGCS ;
00088 volatile UINT32    D_LLUE       ;
00089 int r11[54] ;
00090 volatile UINT32    LINT_EN      ;
00091 volatile UINT32    LINT_STAT    ;
00092 volatile UINT32    LINT_MAP0    ;
00093 volatile UINT32    LINT_MAP1    ;
00094 volatile UINT32    VINT_EN      ;
00095 volatile UINT32    VINT_STAT    ;
00096 volatile UINT32    VINT_MAP0    ;
00097 volatile UINT32    VINT_MAP1    ;
00098 volatile UINT32    STATID       ;
00099 volatile UINT32    V1_STATID    ;
00100 volatile UINT32    V2_STATID    ;
00101 volatile UINT32    V3_STATID    ;
00102 volatile UINT32    V4_STATID    ;
00103 volatile UINT32    V5_STATID    ;
00104 volatile UINT32    V6_STATID    ;
00105 volatile UINT32    V7_STATID    ;
00106 volatile UINT32    LINT_MAP2 ;
00107 volatile UINT32    VINT_MAP2 ;
00108 volatile UINT32    MBOX0 ;
00109 volatile UINT32    MBOX1 ;
00110 volatile UINT32    MBOX2 ;
00111 volatile UINT32    MBOX3 ;
00112 volatile UINT32    SEMA0 ;
00113 volatile UINT32    SEMA1 ;
00114 
00115 int r12[40] ;
00116 volatile UINT32    MAST_CTL     ;
00117 volatile UINT32    MISC_CTL     ;
00118 volatile UINT32    MISC_STAT    ;
00119 volatile UINT32    USER_AM      ;
00120 int r13[700] ;
00121 volatile UINT32    VSI0_CTL     ;
00122 volatile UINT32    VSI0_BS      ;
00123 volatile UINT32    VSI0_BD      ;
00124 volatile UINT32    VSI0_TO      ;
00125 int r14 ;
00126 volatile UINT32    VSI1_CTL     ;
00127 volatile UINT32    VSI1_BS;
00128 volatile UINT32    VSI1_BD;
00129 volatile UINT32    VSI1_TO;
00130 int r15 ;
00131 volatile UINT32    VSI2_CTL;
00132 volatile UINT32    VSI2_BS;
00133 volatile UINT32    VSI2_BD;
00134 volatile UINT32    VSI2_TO;
00135 int r16 ;
00136 volatile UINT32    VSI3_CTL;
00137 volatile UINT32    VSI3_BS;
00138 volatile UINT32    VSI3_BD;
00139 volatile UINT32    VSI3_TO;
00140 int r17[6] ;
00141 volatile UINT32    LM_CTL ;
00142 volatile UINT32    LM_BS ;
00143 int r177 ;
00144 volatile UINT32    VRAI_CTL;
00145 volatile UINT32    VRAI_BS;
00146 int r18[2] ;
00147 volatile UINT32    VCSR_CTL;
00148 volatile UINT32    VCSR_TO;
00149 volatile UINT32    V_AMERR;
00150 volatile UINT32    VAERR;
00151 volatile UINT32    VSI4_CTL     ;
00152 volatile UINT32    VSI4_BS      ;
00153 volatile UINT32    VSI4_BD      ;
00154 volatile UINT32    VSI4_TO      ;
00155 int r144 ;
00156 volatile UINT32    VSI5_CTL     ;
00157 volatile UINT32    VSI5_BS;
00158 volatile UINT32    VSI5_BD;
00159 volatile UINT32    VSI5_TO;
00160 int r154 ;
00161 volatile UINT32    VSI6_CTL;
00162 volatile UINT32    VSI6_BS;
00163 volatile UINT32    VSI6_BD;
00164 volatile UINT32    VSI6_TO;
00165 int r164 ;
00166 volatile UINT32    VSI7_CTL;
00167 volatile UINT32    VSI7_BS;
00168 volatile UINT32    VSI7_BD;
00169 volatile UINT32    VSI7_TO;
00170 
00171 int r19[5] ;
00172 volatile UINT32    VCSR_RES ;
00173 volatile UINT32    VCSR_CLR;
00174 volatile UINT32    VCSR_SET;
00175 volatile UINT32    VCSR_BS ;
00176 
00177 } ;
00178 
00179 
00180 
00181 #endif  /*  _UNI_LIB_H */