RTS/include/SECTOR/sectorMemMap.h

// MZ maps

// memory
#define MZ_MEM_BASE_ADDR_CPU_C          0xE0000000
#define MZ_MEM_BASE_ADDR_CPU_NC         0xF0000000
#define         MZ_SDRAM_OFF                    0x00400000
#define         MZ_VRAM_OFF                     0x00000000


// PLX regs.
#define MZ_PLX_BASE_ADDR_CPU            0xA0000000

// PCI region
#define MZ_PCI_BASE_ADDR_CPU            0x00000000

// Control region
#define MZ_CNTRL_BASE_ADDR_CPU          0xC0000000
#define         MZ_ASIC_OFF                     0x00000000
#define         MZ_ASIC_BUFFER                  0x00000200
#define         MZ_ASIC_INT                     0x00000204
#define         MZ_VRAM_WPBM                    0x00000400
#define         MZ_SER_CLEAR                    0x00000404
#define         MZ_SER_ISSUE                    0x0000040C

// RB maps

#define RB_CNTRL_BASE_ADDR_PCI  0x12000000
#define         RB_RB_VRAM_OFF          0x00000000
#define         RB_RB_CNTRL_OFF         0x00008000
#define                 CLR_BSY_0       0x00000000
#define                 CLR_BSY_1       0x00000004
#define                 CLR_BSY_2       0x00000008
#define                 LVL_BSY_0       0x00000010
#define                 LVL_BSY_1       0x00000014
#define                 LVL_BSY_2       0x00000018
#define                 FEND_CLR        0x00000020
#define                 FEND_STAT       0x00000024
#define                 FEND_ERR        0x00000028
#define                 SVT_MODE        0x0000002C
#define         RB_MZ0_CNTRL_OFF        0x00010000
#define         RB_MZ1_CNTRL_OFF        0x00020000
#define         RB_MZ2_CNTRL_OFF        0x00030000
#define         RB_RB_PLX_OFF           0x00040000
#define         RB_MZ0_PLX_OFF          0x00050000
#define         RB_MZ1_PLX_OFF          0x00060000
#define         RB_MZ2_PLX_OFF          0x00070000
#define         RB_RB_UNI_OFF           0x00080000

#define RB_MEM_BASE_ADDR_PCI    0x10000000
#define         RB_RB_SDRAM_OFF         0x00000000
#define         RB_MZ0_MEM_OFF          0x00800000
#define         RB_MZ1_MEM_OFF          0x01000000
#define         RB_MZ2_MEM_OFF          0x01800000


// PCI configuration cycles

#define RB_PCICFG_UNI_OFFSET    0x00000800
#define RB_PCICFG_PLX_OFFSET    0x00001000
#define RB_PCICFG_MZ0_OFFSET    0x00001800
#define RB_PCICFG_MZ1_OFFSET    0x00002000
#define RB_PCICFG_MZ2_OFFSET    0x00002800

// RB to VME maps
#define RB_SB_MEM_BASE_PCI      0x00000000


// VME->RB mapping 

#define RB_MEM_BASE_ADDR_VME    0x10000000
#define RB_MEM_BASE_ADDR_MAP    0x10000000
#define RB_MEM_OFFSET_VME       0x02000000

#define RB_CNTRL_BASE_ADDR_VME  0x28000000
#define         RB_CNTRL_PCICFG_OFFSET_VME      0x00090000
#define RB_CNTRL_BASE_ADDR_MAP  0x12000000

#define RB_CNTRL_OFFSET_VME     0x00100000

---