Here all ladders still means without ladder7 and ladder8 (identified before as dead ladders)
Figure 1 : all ladders.
ladders
Comments
I get before an efficiency of 60 % because I took into account all the ladders (but still without ladder7 and 9)
When i do the same ladder by ladder, we see that there is still few ladders that decrease the overall efficiency but for a good ladder (ladder 11), efficiency is ~ 80 % and is pretty flat with P.
ladders
Here is the charge matching for hits in SSD : each panel is for the 16 wafers per ladder.
The blue line symbolizes the perfect matching (pulse N = pulseP) and the red line is linear correlation (pulseN = a * pulseP +b from the fit from the 2-d plot)
I select 4 ladders (with differents behaviours) from plots above and compare with the efficiency for a recent production (auau200 upgr 07, where there is a perfect SSD, ie noise and pedestal are fixed for all the strips).