/* HDLC mezzanine target addresses and other hardware parameters - PART A - for configuration memory accesses */ #define CSR3_OPTION_ADDR 0x70083e /* address for CS3 option control register */ #define CSR3_OPTION_NORMAL 0xfe00 /* CS3 option register value for normal operation */ #define CSR3_OPTION_INTERNAL_DTACK 0x1e00 /* CS3 option register value for internal DTACK, no wait states */ #define CM_REG_ADDR 0x020000 /* address for CM reg (NOTE: only when set up properly!) */ #define CM_REG_WE_N_MASK (OUTBIT1) /* mask for IO bit connected to CM_REG_WE_N */ #define CM_REG_OE_N_MASK (OUTBIT2) /* mask for IO bit connected to CM_REG_OE_N */ #define FPGA_PROG_N_MASK (OUTBIT4) /* mask for IO bit connected to PROGRAM_N */ #define PWR_TRIP_N_MASK (INBIT1) /* mask for IO bit connected to PWR_TRIP_N */ #define CMDOUT_MASK (INBIT2) /* mask for IO bit connected to CMDOUT */ #define FPGA_INIT_N_DONE_N_MASK (INBIT3) /* mask for IO bit connected to INIT_N/DONE_N */ #define FPGA_DONE_MASK (INBIT4) /* mask for IO bit connected to DONE */ #define CM_OPCODE_PAGE_PROG_BUF_ONE 0x82 /* AT45DB021 opcode for page program through buffer 1 */ #define CMCS_N_MASK 0x0001 /* mask for CM reg bit connected to CS_N */ #define CMCLK_MASK 0x0002 /* mask for CM reg bit connected to CLK */ #define CMDIN_N_MASK 0x0004 /* mask for CM reg bit connected through inverter to DIN */ #define CMREG_DEFAULTS ((CMCS_N_MASK)|(CMCLK_MASK)) /* HDLC mezzanine target addresses and other hardware parameters - PART B - for all other accesses (normal use) */ #define BOXID_ADDR 0x022000 /* address of box id register (two words) */ #define CSR_ADDR 0x022004 /* address of RDO board CSR */ #define PULSER_TRIG_LATENCY_ADDR 0x022006 /* address of pulser to readout trigger latency register */ #define BOX_DELAY_ADDR 0x022010 /* address of box delay (i.e. overall clock delay) register */ #define RESET_DELAY_ADDR 0x022012 /* address of reset delay register */ #define RESET_WIDTH_ADDR 0x022014 /* address of reset width register */ #define MON_CP_TEMP_ADDR 0x023014 /* address of center plate temperature */ #define MON_RDO_TEMP_ADDR 0x023016 /* address of readout board temperature */ #define MON_FEE_A_TEMP_ADDR 0x023018 /* address of FEE board A (0-23, as may be selected) temperature */ #define MON_FEE_B_TEMP_ADDR 0x02301a /* address of FEE board B (24-47, as may be selected) temperature */ #define FEE_BASE_ADDR 0x020000 /* base address of FEE board space */ #define FEE_BLOCK_SIZE_BYTES 0x000080 /* each FEE board address space size in BYTES */ #define FEE_READBUF_OFFSET 0x000000 /* offset of FEE board readout buffer */ #define FEE_READBUF_SIZE_BYTES 0x000076 /* size of READBUF address space in BYTES (actual READBUF is half as many!) */ /* NOTE: the code may use block read/write, relying implicitly on the order & value of the following offsets */ #define FEE_LATENCY_OFFSET 0x000076 /* offset of latency register - SEE NOTE */ #define FEE_PCR0_OFFSET 0x000078 /* offset of pulser control register MSB - SEE NOTE */ #define FEE_PCR1_OFFSET 0x00007a /* offset of pulser control register LSB - SEE NOTE */ #define FEE_CSR_OFFSET 0x00007c /* offset of FEE board CSR - SEE NOTE */ #define FEE_BOARD_ID_OFFSET 0x00007e /* offset of FEE board id register - SEE NOTE */ #define FEE_CSR_TEMP_ENABLE_MASK 0x01 /* mask for temperature output enable bit in FEE board CSR */ #define FEE_CSR_DATA_ENABLE_MASK 0x02 /* mask for normal readout data enable bit in FEE board CSR */ #define FEE_CSR_SYNC_ERR_MASK 0x04 /* mask for sync error bit in FEE board CSR (CLEARED ON READ!) */ #define FEE_CSR_PREPOST_MASK 0x08 /* mask for pre/post readout enable bit in FEE board CSR */ /* software etc. parameters */ #define MAX_WORDS_WRITE 1000 /* maximum number of words to use in block write */ #define BUF_MAX 100 /* general-purpose inbuf size */ #define NPRINT 6 /* number of words to print on screen during page download */ STATUS smdCheckStatus(int net_num, UINT8 net_node, UINT16 *pwr_trip_n, UINT16 *done, UINT16 *init_n_done_n); int check_response(UINT16 response); STATUS pageProgram(int net_num, UINT8 net_node, UINT16 page_addr); STATUS smdConfigDownload(int net_num, UINT8 net_node, char *infileName, UINT16 page_addr); STATUS smdReConfig(int net_num, UINT8 net_node); STATUS smdSetBoxDelay(int net_num, UINT8 net_node, int dacValue); STATUS smdSetResetDelay(int net_num, UINT8 net_node, int dacValue); STATUS smdSetResetWidth(int net_num, UINT8 net_node, int dacValue); STATUS smdEnablePulser(int net_num, UINT8 net_node, int chan, int amplitude); STATUS smdDisablePulser(int net_num, UINT8 net_node, int chan); STATUS smdEnableAllPulser(int net_num, UINT8 net_node, int amplitude); STATUS smdDisableAllPulser(int net_num, UINT8 net_node); STATUS smdRead(int net_num, UINT8 net_node, UINT32 addr, UINT16 *data); STATUS smdMonitor(int net_num, UINT8 net_node); void write_boxMonitorLog(void); STATUS smdLoopMonitor(int net_num, UINT8 net_node); STATUS smdSetAllControls(int net_num, UINT8 net_node); STATUS smdSetOneFeeCsr(int net_num, UINT8 net_node, int fee_num); STATUS smdInit(int net_num, UINT8 net_node); STATUS readData(int net_num, UINT8 net_node, char *label, BOOL write_it, int count); void setReportFlag(); STATUS readDataForever(int net_num, UINT8 net_node); STATUS loopPulseTimeReadData(int net_num, UINT8 net_node, double t0, double t1, double delta_t, int count); STATUS loopResetWidthReadData(int net_num, UINT8 net_node, int t0, int t1, int delta_t, int count); STATUS loopResetDelayReadData(int net_num, UINT8 net_node, int t0, int t1, int delta_t, int count);