DAQ interface: A typical minimum ionizing particle in the SDD produces a cluster of about 40 pixels (via anode charge sharing and distribution in time). In a central Au+Au collision, an average of about 2000 charged particles cross the three layers of the SVT. Thus, the equivalent occupancy in the detector is approximately 3% or less than 1 Mega-word of data.
The 20 Mega-words of unsuppressed ADC information forming one event will be transmitted to the DAQ at a rate of 100 Hz. The data will be filtered (zero suppressed) with customized Application Specific Integrated Circuits (ASIC) to reduce the rate to 1 Mega-word.
The SVT/DAQ interface is designed in accordance to the TPC/DAQ interface. Most components are adapted with minor modifications. A fiberlink connects the RDO board to the receiver board located in the counting house. The transmission rate is optimized based on the present capabilities of an SCI fiberlink. The receiver board houses the ASIC and a microprocessor to apply waveform analysis and cluster finding for further data reduction. Data are available to the trigger in time for a third level trigger decision.
Trigger interface: The trigger interfaces to the SVT timing and control board at the TPC sectors. Upon receipt of a zeroth level trigger, based on vertex information from the vertex position detector (VPD), the SVT DAQ will start processing. The trigger interface also provides non-physics trigger such as an 'empty' trigger (MT) and a calibration trigger (CT). The MT starts an event for the purpose of pedestal recording. It has to start the complete set of detectors to document the effect of the neighboring detectors on the SVT pedestal (in particular the effect of the TPC gated grid).
The CT sends a calibration pulse to the 6 charge injection lines on each SDD. The detector response to this signal will be used for gain equilibration and calibration. Both MT and CT information (pedestal and gain) will be accessible in the memory of the DAQ-ASIC to filter the unsuppressed SVT data.
The trigger interface also provides the timing for all frontend components, synchronized to the RHIC beam crossing frequency. Every FEE clock rate is an integer multiple of the RHIC clock.
Provision of third level trigger information from the SVT receiver card to the trigger micro processor is possible and applications are under investigation.
Slow Controls Interface: The following parameters will be monitored by the slow controls interface:
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