FRONT PAGE, INTRODUCTION, MODEL DESCRIPTION, RESULTS, CONCLUSION, FUTURE
Clearly the model is only in a preliminary stage. There are many functions,
methods, objects etc. which could be envisioned as upgrades to the
present simulation. Here are a few which are currently in the works:
Please send any questions or comments on possible simulation additions to
J.P.Whitfield, Carnegie Mellon, 4/20/95
- It is planned that an object which can handle various mixtures
of event types, with various collision distributions will be added
to the RHIC object. This will allow the study of deadtime as related
to mixtures of event rates, which will be crucial to understanding
the trigger data flow response in p-p running.
- A new token scheme in which upon acceptance of an event by Level 1
analysis, the Level 1 Que Manager will add a new token to the tokenQue.
Simulation of this technique for throttle in the trigger will
help provide information concerning latencies for events with respect
to other throttle methodologies.
- Additions of Level 3 and Level 4 analysis objects. This will help
provide a more true representation of token management and detector
deadtime, as affected by DAQ busy, for instance. Currently there is no
mechanism for DAQ busy, for instance when the ASIC has 14 events in its
queue. This is clearly necessary for a more accurate model and simualtion
and will be included in the L3/4 objects. The Trigger/DAQ interface and
latencies related with this interface will also be incorporated in these
Inclusion of input variables for CPU Loading time and distribution
for Levels 1 and 2. This will provide a more "realistic" latency result,
whereas currently the worst case scenario for the maximum input rate
at the given trigger levels is incorporated.
Inclusion of a distribution of times to WAIT for a HUNG event in
Level 1 and Level 2 Cpu's.
Inclusion of a rejection factor for events which hang in Level 1 and 2
analysis. In conjunction with these additions a REBOOT METHOD will
be included for particular HANG states in the CPU's.