StRoot  1
stage_3_201900.cxx
1 #include <stdio.h>
2 #include <sys/types.h>
3 #include <string.h>
4
5 #include "fcs_trg_base.h"
6
7 //#include "fcs_trg_201901.h"
8
9 // And the last stage where North and South are combined.
10 // Output is a 12 bit value (max) which goes into STAR Trigger
11 // either LastDSM, RAT, TCU, etc.
12
13 // Tonko: it goes first into the RAT and then to the LastDSM
14
16 {
17  *dsm_out = 0;
18
19  // Tonko: it is link[2] in FY19 (South, first) and not link[1]
20  // as it was in the original code
21  // Tonko: also, why ">0"??
22
23  if((link[2].d[0] & 0x07)>0) *dsm_out |= 0x1;
24  if((link[2].d[0] & 0x38)>0) *dsm_out |= 0x2;
25  if((link[2].d[1] & 0x07)>0) *dsm_out |= 0x4;
26  if((link[2].d[1] & 0x38)>0) *dsm_out |= 0x8;
27  if((link[2].d[2] & 0x07)>0) *dsm_out |= 0x10;
28  if((link[2].d[2] & 0x38)>0) *dsm_out |= 0x20;
29  if((link[2].d[3] & 0x07)>0) *dsm_out |= 0x40;
30  if((link[2].d[3] & 0x38)>0) *dsm_out |= 0x80;
31  if((link[2].d[4] & 0x01)>0) *dsm_out |= 0x100;
32  if((link[2].d[4] & 0x02)>0) *dsm_out |= 0x200;
33
34  //Tonko: use 12th bit
35  if(link[2].d[7] & 0x80) *dsm_out |= 0x800;
36
37
38  // Tonko: slighly modified so I can run GEANT emulation.
39  // This part is ignored in FY19 VHDL since it didn't exist anyway
40
41  if((link[0].d[0] & 0x07)>0) *dsm_out |= 0x1;
42  if((link[0].d[0] & 0x38)>0) *dsm_out |= 0x2;
43  if((link[0].d[1] & 0x07)>0) *dsm_out |= 0x4;
44  if((link[0].d[1] & 0x38)>0) *dsm_out |= 0x8;
45  if((link[0].d[2] & 0x07)>0) *dsm_out |= 0x10;
46  if((link[0].d[2] & 0x38)>0) *dsm_out |= 0x20;
47  if((link[0].d[3] & 0x07)>0) *dsm_out |= 0x40;
48  if((link[0].d[3] & 0x38)>0) *dsm_out |= 0x80;
49  if((link[0].d[4] & 0x01)>0) *dsm_out |= 0x100;
50  if((link[0].d[4] & 0x02)>0) *dsm_out |= 0x200;
51
52  //Tonko: use 12th bit
53  if(link[0].d[7] & 0x80) *dsm_out |= 0x800;
54
55
56
57  if(fcs_trgDebug>=1) printf("FCS STG3 output = %04x\n",*dsm_out);
58
59 }
60