From: W.J. Llope (llope_at_physics.rice.edu)
Date: Mon Feb 03 2003 - 14:50:54 EST
hello folks - please read the whole thing - there's some action
items.... thanks. (comments please)
cheers
----------------------------------------------------------
summary of 1/29/03-1/30/03 access
lijuan ruan, johan gonzalez, bill llope
goals:
A: specific adc/tdc mapping problem in tofr - must locate & fix!
B: scattered problem channels in TOFp that could be fixed given
the opportunity.... when this travel was booked there was no intention
to address the scattered failed chs in tofp, but (!):
C: tofp "died" literally the night before i was to come out
anyway -> must fix!
discussing these in reverse order, here's how it went...
----- Area C: dead tofp.
upon repowering the LV under supervision it was clear that the + side
was pegged at the front panel current limit, which i had set at ~1A above the
expected value -> no doubt at all that there was a significant FEE problem.
i then divided-and-conquered (took a while!) and determined that the
entire effect was due to fee posn #1
-> replaced FEE board #1 with FEE #2.
total bus currents then back to normal (modulo other
problems- see below).
goal C thus done. this board (and others - see below) are unfortunately
out at BNL in the cabinet. i'm going to ask frank to box these
up and ship them to rice when he's out there...
----- Area B: scattered tofp problem chs even before 'the death'
the usual. some are cells, some are bad fee...
after fixing the dead tofp problem, wednesday night was spent using
the pulser at the tofp fee inputs and looking for signals at the tofp
(a/t)dc inputs... after this:
identified three channels almost certainly hobbled by bad cells...
(frank also coordinated on this) -> these were replaced early thursday
morning: ("slats" here are numbered 1-41 inclusive)
slat 16 HVC 30 -> HVC 29
slat 19 HVC 37 -> HVC 50
slat 39 HVC 19 -> HVC 24
amazingly, i was able to get the nederlander to wake up at
8am central thursday to test the new cells. all cells then appeared to be
alive.
from the rest of wednesday night's strobe testing:
one of the bad channels in TOFp (#4, tdc but no adc) was fixed by the
replacement of FEE posn #1 (already dealt with - see above).
FEE posn #9 was just dead -> replaced (board #7 out, #13 in).
slat 9 showed an adc output at the fee that was ringy/ugly
-> replaced (board #4 out, board #14 in).
slat 12 - adc and tdc outputs fine at fee output, also saw good signals
at the (a/t)dc inputs -> no action taken (?!?)
slat 16 - fee to (a/t)dc inputs o.k. - must be cell -> cell replaced.
slat 19 - fee to (a/t)dc inputs o.k. - must be cell -> cell replaced.
slat 22 - no tdc at fee output - board problem - couldn't replace
since out of boards...
slat 32 - adc/tdc o.k. at fee output but no signal at plat disc. ->
presume failed B section. attemped disassemble/clean/resolder
the right-angle connector (i.e. the finicky one at
the fee output -
by far the most likely culprit) but didn't help. no time to
trace further.
slat 39 - fee to (a/t)dc inputs o.k. - must be cell -> cell replaced.
slat 37 (INFERENCE - this ch existed in a failed FEE board but i have a
suspicion - this channel and this board have failed before, and to
cut-to-the-chase i suspected a specific mechanical problem which then
lead me to leave this cell unconnected to its appropriate fee input....
==> this cell can be turned off in the hvsys map...
i do not expect
this ch to produce data. i am interested to see if though if i was
able to curcumvent the (?) mechanical problem that was bringing
down all 4 chs in this FEE board before.... we'll see, so far that
board is still UP, whereas in the last two runs it was the first
to fail and did so very early after a tray refurbishing...
THERMOCOUPLES....
reconnected all but one of the missing seven (in and near TOFp), and
these 6 read out real #s now... temperatures on the fee are normal (HOT)
but interior air temps are reasonable, so all this seems o.k. and consistent
w/ run-2.
most of the blood was covered by kapton tape so don't
worry about the bio-hazards. ;-)
----- Area A: tofr "mapping problem".
an aside to start. the fact that we have and are powering
more active detector channels than readout channels in tofr is a
unique feature of this system....
(who on earth would install more detector chs than
they can read out?!? nutty!). the problem is that there is a certain class
of cabling problems, e,g, b+c vs d mismatches, where one can see absolutely
valid signals at the (a/t)dc inputs yet there's still a mapping problem
since these signals "aren't coming from the same modules"....
in previous emails i showed that there was an apparent mismatch
between the tofr adc and tdc mapping -> i had found two software
solutions which
lead to a correct (a/t)dc matching for all but a handful of tofr chs...
these software solutions, i.e. the ch-number locations of the "missing" chs,
were naturally expected to help us locate what we thought was a simple
B vs C or B-C vs D or Aeven vs Aodd vs B-C vs D, or whatever, cabling problem.
hmmmmmmm.
bottom line is that during this access there were no changes made
to fix any tofr cabling problem. all the cabling looks o.k.!
we found one bad tofr discriminator - fixed. lijuan knows what
channel it is.... lijuan?
lijuan and johan did a very careful job and rechecked all the
cabling starting from the pigtails and up to the digitizers.
they will be sending around some detailed maps shortly.
summarizing all this:
- there are valid logic or mrpc signals from the detectors seen
at the digitizer inputs in all the ch-number-areas where the 2 software
maps indicates there may be the "cabling" problem. i.e.
good signals are getting to the front panels of the digitizers
everywhere.
- the mapping of the B->C cables, which is performed at
the input and output, respectively, of the platform discriminators
is _correct_ according to the cable map set up by Katy & The Daniels.
- the mapping of C cables to tdc inputs is _correct_
- the mapping of D cables to adc inputs is _correct_
- the mapping of A(odd) cables to B cables at the pole-tip is
_consistent_ with the mapping of A(even) cables to D cables...
i.e. no apparent mismatches at the pigtail->B/D junctions was
seen.
i.e. the cabling looks rock solid. please take a look
at the maps that lijuan and johan send around....
overall summary:
C: successful
B: successful
A: we're stumped. but more info in hand now, and more
to come shortly....
--W.J. Llope, Ph.D. Res. Assoc. Professor T.W. Bonner Nuclear Laboratory phone: 713-348-4741 Rice University, MS-315 fax: 713-348-5215 6100 S. Main St. Houston, TX 77005-1892 e-mail: llope_at_physics.rice.edu WWW home: http://wjllope.rice.edu/default.html
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