Last modified: 7-OCT-1999
TPC pedestal rms is usually evaluated individually for each of 512 time buckets per channel. The last time bucket shows excessive rms and will probably not be used. On occasion, the first three time buckets also exhibit excessive rms; this is not expected to cause problems, since the gating grid will also cause noise in the early time bins.
In general, the TPC pedestal rms is of order 1 ADC count, but can be considerably higher: the noise is a function of input capacitance, grounding quality, noise pickup, etc. Shorted pads can have large rms.
The first pedestal event of a run should currently be ignored, since pedestals can drift upwards by several ADC counts, if the system has been idle for a few minutes; this atypical event will drive the calculated rms up considerably.
FEE noise is mostly series, not parallel; it is shaped by the derivative of the pulse shaping function, not the 180-ns-wide shaping function itself. Therefore, correlations between adjacent time buckets are small--and often negative. This has not been adequately studied for the production electronics.
For 20 pre-production FEE boards, noise tended to be highly correlated with the 16 channels grouped on a pair of SAS/SCA chips. This has not been adequately studied for the production electronics.
For 20 pre-production FEE boards, there was some noise correlation between channel within a given FEE, even when not on the same chip. This has not been adequately studied for the production electronics.
For 20 pre-production FEE boards, there was little or no noise correlation with channels on other FEE boards. This has not been adequately studied for the production electronics.
Unchecked. Capacitance measurements exist for the outer sector (but not for the inner one).
For the test subsectors, the noise is clearly larger along the edges and at the other corners. Some of this is due to larger printed circuit trace capacitance in these areas, but there seem to be additional effects.
Unchecked for the production FEE cards.